• Volume/Page
  • Keyword
  • DOI
  • Citation
  • Advanced
   
 
 
 

Facebook Podcast Flickr Twitter UniPHY Group iResearch App

FULL-TEXT OPTIONS:

J. Renewable Sustainable Energy 1, 053102 (2009); doi:10.1063/1.3204460 (15 pages)

A novel pulse width modulation for grid-connected multilevel inverter

J. Selvaraj and N. A. Rahim

Department of Electrical Engineering, University Malaya, 50603 Kuala Lumpur, Malaysia

View MapView Map

(Received 6 October 2008; accepted 23 July 2009; published online 18 September 2009)

This paper presents a single-phase five-level grid-connected photovoltaic inverter with a novel dual reference modulation technique. Two reference signals identical to each other with an offset equivalent to the amplitude of the triangular carrier signal were used to generate pulse width modulation (PWM) signals. The inverter consists of a full-bridge inverter and an auxiliary circuit comprising of four diodes and a switch. The inverter produces output voltage in five levels: 0, +1/2Vdc, Vdc, −1/2Vdc, and Vdc. A digital proportional-integral (PI) current control algorithm is implemented in DSP TMS320F2812 to keep the current injected into the grid sinusoidal and to have high dynamic performance with low total harmonic distortion (THD). The validity of the proposed inverter is verified through simulation and is implemented in a prototype. The experimental results are compared to conventional single-phase three-level grid-connected pulse width modulation (PWM) inverter in terms of THD.

© 2009 American Institute of Physics

Article Outline

  1. INTRODUCTION
  2. FIVE-LEVEL INVERTER TOPOLOGY
  3. PWM MODULATION AND OPERATIONAL PRINCIPLE
  4. CONTROL SYSTEM ALGORITHM AND IMPLEMENTATION
  5. SIMULATION RESULTS
  6. EXPERIMENTAL RESULTS
  7. CONCLUSION

KEYWORDS and PACS

PACS

  • 84.70.+p

    High-current and high-voltage technology: power systems; power transmission lines and cables

  • 84.60.Jt

    Photoelectric conversion

  • 88.40.mp

    Grid-tied solar electric systems

  • 84.30.Jc

    Power electronics; power supply circuits

PUBLICATION DATA

ISSN:

1941-7012 (print)  
1941-7012 (online)

  1. N. A. Rahim and S. Mekhilef, Proceedings of IEEE Power Conference, October 2002, Vol. 1, pp. 570–573.
  2. S. Kouro, J. Rebolledo, and J. Rodriguez, IEEE Trans. Ind. Electron. 54, 2894 (2007).
  3. S. J. Park, F. S. Kang, M. H. Lee, and C. U. Kim, IEEE Trans. Power Electron. 18, 831 (2003). [Inspec]
  4. L. M. Tolbert and T. G. Habetler, IEEE Trans. Ind. Appl. 35, 1098 (1999). [Inspec]
  5. M. Calais, L. J. Borle, and V. G. Agelidis, IEEE 32th Annual Power Electronics Specialists Conference 2001 (PESC '01), 17–21 June 2001, Vol. 3, pp. 1173–1178.
  6. N. S. Choi, J. G. Cho, and G. H. Cho, IEEE 22th Annual Power Electronics Specialists Conference 1991 (PESC '91), 24–27 June 1991), pp. 96–103.
  7. G. Carrara, S. Gardella, M. Marchesoni, R. Salutari, and G. Sciutto, IEEE Trans. Power Electron. 7, 497 (1992).
  8. J. Selvaraj and N. A. Rahim, IEEE Trans. Ind. Electron. 56, 149 (2009). [Inspec]
  9. V. G. Agelidis, D. M. Baker, W. B. Lawrance, and C. V. Nayar, Proceedings of IEEE ISIE '97, Guimaraes, Portugal, 1997, pp. 589–594.
  10. M. H. Rashid, in Power Electronics: Circuits, Devices, and Applications, 3rd ed., Pearson Prentice Hall, 2004, p. 267.
  11. T. Esram and P. L. Chapman, IEEE Trans. Energy Convers. 22, 439 (2007).
  12. N. Femia, G. Petrone, G. Spagnuolo, and M. Vitelli, IEEE 35th Annual Power Electronics Specialists Conference 2004 (PESC '04), 20–25 June 2004, Vol. 3, pp. 1939–1944.
  13. X. Liu and L. A. C. Lopes, IEEE 35th Annual Power Electronics Specialists Conference 2004 (PESC '04), 20–25 June 2004, Vol. 3, pp. 2005–2010.

Figures (18) Tables (3)

Figures (click on thumbnails to view enlargements)

FIG.1
Full-bridge inverter configuration together with an auxiliary circuit.

FIG.1 Download High Resolution Image (.zip file) | Export Figure to PowerPoint

FIG.2
Carrier and reference signals.

FIG.2 Download High Resolution Image (.zip file) | Export Figure to PowerPoint

FIG.3
Single-phase five-level inverter topology.

FIG.3 Download High Resolution Image (.zip file) | Export Figure to PowerPoint

FIG.4
Switching pattern for single-phase five-level inverter.

FIG.4 Download High Resolution Image (.zip file) | Export Figure to PowerPoint

FIG.5
MPPT flowchart.

FIG.5 Download High Resolution Image (.zip file) | Export Figure to PowerPoint

FIG.6
Five-level inverter with control algorithm implemented in DSP TMS320F2812.

FIG.6 Download High Resolution Image (.zip file) | Export Figure to PowerPoint

FIG.7
PWM switching strategy.

FIG.7 Download High Resolution Image (.zip file) | Export Figure to PowerPoint

FIG.8
PWM signal for S2–S6.

FIG.8 Download High Resolution Image (.zip file) | Export Figure to PowerPoint

FIG.9
Inverter output waveform for M>1.0: (a) Vinv and (b) Ig.

FIG.9 Download High Resolution Image (.zip file) | Export Figure to PowerPoint

FIG.10
Inverter output waveform for Vinv<Vg/math: (a) Vinv and (b) Ig.

FIG.10 Download High Resolution Image (.zip file) | Export Figure to PowerPoint

FIG.11
Inverter output waveform for Vinv<Vg/math and M<1.0: (a) Vinv and (b) Ig.

FIG.11 Download High Resolution Image (.zip file) | Export Figure to PowerPoint

FIG.12
Prototype of the five-level inverter with dual reference modulation technique.

FIG.12 Download High Resolution Image (.zip file) | Export Figure to PowerPoint

FIG.13
PWM switching signals for S2–S6: (a) S2, (b) S3 and S4, and (c) S5 and S6.

FIG.13 Download High Resolution Image (.zip file) | Export Figure to PowerPoint

FIG.14
Experiment results of Vinv and Ig.

FIG.14 Download High Resolution Image (.zip file) | Export Figure to PowerPoint

FIG.15
Experiment results of Vinv and Ig for Vinv<Vg/math.

FIG.15 Download High Resolution Image (.zip file) | Export Figure to PowerPoint

FIG.16
THD result of five-level PV inverter.

FIG.16 Download High Resolution Image (.zip file) | Export Figure to PowerPoint

FIG.17
Grid voltage Vg and grid current Ig at near unity power factor.

FIG.17 Download High Resolution Image (.zip file) | Export Figure to PowerPoint

FIG.18
THD result of three-level PV inverter.

FIG.18 Download High Resolution Image (.zip file) | Export Figure to PowerPoint

Tables

Table I. Inverter output voltage during S2–S6 switch on and off.

View Table
Table II. PV module characteristics.

View Table
Table III. PV multilevel inverter specifications and controller parameters.

View Table


Close
Google Calendar
ADVERTISEMENT

close